1. Field of the Invention
The present invention relates to a re-configurable circuit capable of realizing a variety of functions programmably and more particularly relates to programmable mutual connection configuration technology suitable for a data path in an operation unit.
2. Description of the Related Art
Today a re-configurable circuit whose hardware can be re-configurated by a program is proposed. Generally the re-configurable circuit has a structure in which a plurality of so-called operation units for processing data is provided in an array.
FIG. 1 shows an example of the configuration of a re-configurable circuit. The re-configurable circuit comprises a plurality of clusters, which are connected by, for example, a crossbar switch or the like and enables the data transfer between the clusters. One cluster comprises an ALU array unit (operator group 2). The ALU array unit comprises a plurality of operation units. The operation unit 10 usually comprises an ALU, a multiplier and the like.
The cluster 1 comprises an operator group 2 (ALU array unit), configuration memory 3 (setting memory) and a sequencer 4.
The operator group 2 comprises a data input unit 5, a data buffer unit 6, a data buffer control unit 7, an inter-operator network 8, data memory 9 and operation units 10.
The data input unit 5 supplies externally inputted data to the data memory 9, each operation unit 10 and the like via the inter-operator network 8. For example, the data input unit 5 comprises the data buffer unit 6. In this case, the data buffer unit 6 selects the buffering/non-buffering of externally inputted data by a control signal from the data buffer control unit 7. The data buffer control unit 7. The data buffer control unit 7 receives configuration information from the configuration memory 3, transmits a control signal to the data buffer unit 6 as the control signal according to the information, and selects the buffering/non-buffering of the input data.
The inter-operator network 8 is mutually connected with a variety of components (such as the data input unit 5, data memory 9, operation unit 10 and the like). The inter-operator network 8 enables the data transfer between a variety of components connected to the inter-operator network 8 according to configuration information generated based on externally supplied configuration data (data generated by compiling a program). The data memory 9 records data via the inter-operator network 8. The operation unit 10 is set so as to perform a function related to configuration information by the configuration information.
The configuration memory 3 loads configuration data onto the configuration memory 3 from an external storage device for storing configuration data, which is not shown In FIG. 1, such as a PC or the like (for example, loads using the communication means of the PC). The configuration memory 3 comprises a configuration data loading unit, which is not shown in FIG. 1, and generates/outputs a configuration switching condition signal based on a condition establishing signal (such as a chip-select signal) mainly transmitted from the operation unit 10 of a variety of re-configurable components constituting the operator group 2. For example, the configuration switching condition signal is generated based on the condition establishing signal and configuration data from the configuration memory 3. The sequencer 4 generates the address of the configuration information to be subsequently read by the configuration data based on the switching condition signal.
FIG. 2 shows the configurations of the configuration memory 3 and operation unit 10 of the re-configurable circuit. Next, the data processing of the operation unit 10 is described below.
In order to set each operation unit 10, configuration information is transferred from the configuration memory 3 to each operation unit 10, and each operation unit 10 is set. At this moment, the configuration information also controls connection switching between operation units 10 to set the input data path of each operation unit 10.
According to Patent reference 1, in a re-configurable device having a programmable mutual connecting network suitable for a data path, both input/output of signal transmission between a function cell (for setting a variety of logic functions programmably) and a long-haul horizontal programmable mutual connection channel are performed via a short-haul horizontal programmable mutual connection channel and a programmable switch. By such a configuration, the load of the long-haul horizontal programmable mutual connection channel can be reduced to realize high-speed transmission. A re-configurable device high-speed programmable mutual connecting network which secures sufficient routability using few switching and wiring and especially in which a multi-bit data path can be efficiently implemented is proposed.
However, in a system using a re-configurable circuit in which a plurality of operation units 10 are provided in an array, for example, in the case of the wireless LAN receiving unit shown in FIG. 3, an analog radio frequency (RF) unit 103 down-converts a signal received from an antenna 101 in order to demodulate it, an analog baseband (BB) unit 103 A/D converts it and a digital BB unit 104 demodulate it. In this case, in order to realize the IEEE802.11a PHY exclusive circuit of the digital BB unit 104 by a re-configurable circuit, a latency condition must be severe in rating. Therefore, sometimes a wireless LAN process cannot be realized in a re-configurable circuit.
Such a problem is caused by the data transfer speed (operation cycle) between operation units 10. For example, in a structure where a plurality of operation units 10 are provided in an array, it depends on the data transfer speed from the first-stage operation unit 10 (operation unit 10 for receiving input data) to the most remote operation unit 10 (operation unit 10 for outputting data). In other words, as the number of operation units 10 for performing the operation process increases, its transfer speed decreases.
The operation unit 10 includes a predetermined process delay (FF12: flip-flop). This process delay is always fixed regardless of the complexity (multiplication, addition, AND (logical product), OR (logical sum) and the like) of a command given to the operation unit 10. Therefore, even if it is the repetition of any simple process, its latency (the number of steps of FFs used until the process is completed after data is inputted) increases at every process of the operation unit 10.
The re-configurable circuit on which three operation units 10 are mapped as shown in FIG. 4 is described as an example. Since a FF12 is permanently provided for the interface of the operation unit 10, process delay for three clocks always occurs. This has no relation to the contents of an operation process performed by the operation unit 10 and process delay increases as the number of operation units 10 increases.
In Patent reference 1, although input/output signals are transmitted between the operation unit 10 and a long-haul horizontal programmable mutual connection channel via a short-haul horizontal programmable mutual connection channel and a programmable switch, there is no special description for a mapping method for improving the process speed of the operation unit.
Patent reference 1: Japanese Patent Application No. 2002-76883